Pin reduction through variable duplications and substitutions in a data dependence graph
نویسندگان
چکیده
Due to the packaging problem, the implementation of computing arrays on chips is constrained to certain pin limitation. This paper introduces two basic techniques for pin reduction without lowering computational efficiency in systolic designs. We exhibit the ideas through the synthesis of a systolic array with very few I / O pins for polynomial division.
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عنوان ژورنال:
- Parallel Computing
دوره 10 شماره
صفحات -
تاریخ انتشار 1989